000			01621cam a22002897a 4500
001			0000060776
003			0001
008			070926s2008 nyua 001 0 eng d
020			_a0387764860 (hdbk. : acid-free paper)
020			_a9780387764863 (hdbk. : acid-free paper)
035			_a(OCoLC)ocn183259720
040			_aBTCTA _cBTCTA _dBAKER _dYDXCP _dNLGGC _dIUP _dCUY _dOCLCG _dSTF _dAU@ _dDLC
042			_alccopycat
082	0	4	_a621.381548 _222
084			_a621.381548 _bTEH-N
100	1		_aTehranipoor, Mohammad H., _d1974-
245	1	0	_aNanometer technology designs _h[Book] : _bhigh-quality delay tests / _cMohammad Tehranipoor, Nisar Ahmed.
260			_aNew York, NY : _bSpringer, _cc2008.
300			_axvii, 281 p. : _bill. ; _c25 cm.
520			_aTraditional at-speed test methods cannot guarantee high quality test results as they face many new challenges. Supply noise effects on chip performance, high test pattern volume, small delay defect test pattern generation, high cost of test implementation and application, and utilizing low-cost testers are among these challenges. This book discusses these challenges in detail and proposes new techniques and methodologies to improve the overall quality of the transition fault test.
521			_aAll.
650		0	_aIntegrated circuits _xTesting.
650		0	_aIntegrated circuits _xVery large scale integration.
650		0	_aNanotechnology.
700			_aAhmed, Nisar.
852			_p43954 _911961.22 _h621.381548 TEH-N _bGround Floor _dBooks _t1 _q1-New _aJZL-CUI
999			_c67626 _d67626