000 01297cam a2200313 a 4500
001 0000047473
003 0001
008 081009s2008 nyua ob 001 0 eng d
020 _a9788184895315
035 _a(OCoLC)261324813
040 _aGW5XE
_beng
_cGW5XE
082 0 4 _a621.392
_222
084 _a621.392
_bSPE-S
100 1 _aSpear, Chris
245 1 0 _aSystemVerilog for verification
_h[Book] :
_ba guide to learning the testbench language features /
_cChris Spear.
250 _a2nd ed.
260 _aNew Delhi :
_bSpringer (India),
_c2008.
300 _axxxvi, 429 p. :
_bill. ;
_c25 cm.
365 _a01
_b2,258.48
521 _aAll.
650 0 _aVerilog (Computer hardware description language).
650 0 _aIntegrated circuits
_xVerification.
852 _p34855
_92258.48
_h621.392 SPE-S
_vAllied Book Company
_bGround Floor
_dBooks
_t1
_q2-Good
_aJZL-CUI
521 _aAll.
650 0 _aComputer networks
_xDesign and construction.
650 0 _aBusiness enterprises
_xComputer networks.
650 0 _aSystem analysis.
852 _p58718
_91794.00
_h004.65 OPP-T
_vBrilliant Books Islamabad.
_bGround Floor
_dBooks
_t1
_q1-New
_aJZL-CUI
999 _c64587
_d64587