CMOS multichannel single-chip receivers for multi-gigabit optical data communications [Book] / by Paul Muller and Yusuf Leblebici.

By:

Müller, Paul

Contributor(s):

Material type: Text

TextSeries: Analog circuits and signal processing seriesPublication details: Dordrecht : Springer, c2007.Description: xx, 191 p. : ill. ; 25 cmISBN:

1402059124
9781402059124
9781402059117

Subject(s):

DDC classification:

621.3827 22

Other classification:

621.3827

Summary: This book focuses on optical communications for short and very short distance applications and discusses the monolithic integration of optical receivers with processing elements in standard CMOS technologies. CMOS Multi-Channel Single-Chip Receivers for Multi-Gigabit Optical Data Communications provides the reader with the necessary background knowledge to fully understand the trade-offs in short-distance communication receiver design and presents the key issues to be addressed in the development of such receivers in CMOS technologies. Moreover, novel design approaches are presented. A system-level design methodology allows for the impact analysis of different block specifications and system-wide design optimization. Statistical models are used for design space exploration in the scope of jitter tolerance analysis of clock recovery circuits.

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Holdings
Item type	Current library	Call number	Status	Date due	Barcode	Item holds
Books	Junaid Zaidi Library, COMSATS University Islamabad Ground Floor	621.3827 MUL-C (Browse shelf(Opens below))	Available		45784

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This book focuses on optical communications for short and very short distance applications and discusses the monolithic integration of optical receivers with processing elements in standard CMOS technologies. CMOS Multi-Channel Single-Chip Receivers for Multi-Gigabit Optical Data Communications provides the reader with the necessary background knowledge to fully understand the trade-offs in short-distance communication receiver design and presents the key issues to be addressed in the development of such receivers in CMOS technologies. Moreover, novel design approaches are presented. A system-level design methodology allows for the impact analysis of different block specifications and system-wide design optimization. Statistical models are used for design space exploration in the scope of jitter tolerance analysis of clock recovery circuits.

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