Verification and validation in systems engineering [Book] : assessing UML/SysML design models / Mourad Debbabi ... [et al.].
Material type:
TextPublication details: Heidelberg ; New York : Springer, c2010.Description: xxvi, 248 p. ; 24 cmISBN: - 9783642152283 (e-isbn)
- 9783642152276
- 3642152279
- 004.24 22
- 004.24
| Item type | Current library | Call number | Status | Date due | Barcode | Item holds |
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Junaid Zaidi Library, COMSATS University Islamabad | 004.24 VER (Browse shelf(Opens below)) | Available | 41149 |
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| 004.22 WIL-C Computer systems architecture a nteworking approach / | 004.24 FOR-C Computer systems performance evaluation and prediction | 004.24 SHA-F Forecasting Oracle performance | 004.24 VER Verification and validation in systems engineering assessing UML/SysML design models / | 004.256 HEA-V VMEbus a practical companion / | 004.256 HEA-V VMEbus a practical companion / | 004.256 LAB-E Embedded systems building blocks complete and ready-to-use modules in C / |
Includes bibliographical references (p. 227-239) and index.
Introduction -- Architecture frameworks, model-driven architecture, and simulation -- Unified Modeling Language -- Systems Modeling Language -- Verification, Validation, and accreditation -- Automatic approach for synergistic verification and validation -- Software engineering metrics in the context of systems engineering -- Verification and validation of UML behavioral diagrams -- Probabilistic model checking of SysML activity diagrams -- Performance analysis of time-constrained SysML activity diagrams -- Semantic foundation of SysML activity diagrams -- Soundness of the translation algorithm.
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