MARC details
| 000 -LEADER |
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| fixed length control field |
03549cam a2200325Ii 4500 |
| 001 - CONTROL NUMBER |
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| control field |
0000352370 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
0001 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
220221s2020 sz# ob 001 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9783030382940 (hardback) |
| Qualifying information |
(electronic bk.) |
|
|---|
| Qualifying information |
(electronic bk.) |
|
|---|
| Canceled/invalid ISBN |
9783030382940 |
| Qualifying information |
(print) |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(OCoLC)1136959035 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
EBLCP |
| Language of cataloging |
eng |
| Description conventions |
rda |
| Transcribing agency |
EBLCP |
| Modifying agency |
GW5XE |
| -- |
EBLCP |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.395 |
| Edition number |
23 |
| 084 ## - OTHER CLASSIFICATION NUMBER |
|---|
| Classification number |
621.395 |
| Item number |
LOG |
| Number source |
23 |
| 245 00 - TITLE STATEMENT |
|---|
| Title |
Logic synthesis for FPGA-based control units |
| Medium |
Book : |
| Remainder of title |
structural decomposition in logic design / |
| Statement of responsibility, etc. |
Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Slawomir Chmielewski. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xvi, 247 pages : |
| Dimensions |
24 cm. |
| 365 ## - TRADE PRICE |
|---|
| Price type code |
01 |
| Price amount |
24,553.00 |
| 440 #0 - SERIES STATEMENT/ADDED ENTRY--TITLE |
|---|
| Title |
Lecture notes in electrical engineering ; |
| Authority record control number |
http://id.loc.gov/authorities/names/no2007099709 |
| Volume/sequential designation |
v. 636 |
| 490 1# - SERIES STATEMENT |
|---|
| Series statement |
Lecture Notes in Electrical Engineering ; |
| Volume/sequential designation |
v.636 |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
This book focuses on control units, which are a vital part of modern digital systems, and responsible for the efficiency of controlled systems. The model of a finite state machine (FSM) is often used to represent the behavior of a control unit. As a rule, control units have irregular structures that make it impossible to design their logic circuits using the standard library cells. Design methods depend strongly on such factors as the FSM used, specific features of the logic elements implemented in the FSM logic circuit, and the characteristics of the control algorithm to be interpreted. This book discusses Moore and Mealy FSMs implemented with FPGA chips, including look-up table elements (LUT) and embedded memory blocks (EMB). It is crucial to minimize the number of LUTs and EMBs in an FSM logic circuit, as well as to make the interconnections between the logic elements more regular, and various methods of structural decompositions can be used to solve this problem. These methods are reduced to the presentation of an FSM circuit as a composition of different logic blocks, the majority of which implement systems of intermediate logic functions different (and much simpler) than input memory functions and FSM output functions. The structural decomposition results in multilevel FSM circuits having fewer logic elements than equivalent single-level circuits. The book describes well-known methods of structural decomposition and proposes new ones, examining their impact on the final amount of hardware in an FSM circuit. It is of interest to students and postgraduates in the area of Computer Science, as well as experts involved in designing digital systems with complex control units. The proposed models and design methods open new possibilities for creating logic circuits of control units with an optimal amount of hardware and regular interconnections |
| 521 ## - TARGET AUDIENCE NOTE |
|---|
| Target audience note |
All. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Logic circuits |
| General subdivision |
Design. |
| Authority record control number or standard number |
http://id.loc.gov/authorities/subjects/sh85078116 |
| -- |
http://id.loc.gov/authorities/subjects/sh2002006371 |
|
|---|
| Topical term or geographic name entry element |
Field programmable gate arrays. |
| Authority record control number or standard number |
http://id.loc.gov/authorities/subjects/sh93009062 |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Barkalov, Alexander. |
| Authority record control number or standard number |
http://id.loc.gov/authorities/names/no2009024436 |
|
|---|
| Personal name |
Titarenko, Larysa. |
| Authority record control number or standard number |
http://id.loc.gov/authorities/names/no2009047498 |
|
|---|
| Personal name |
Mielcarek, Kamil. |
| Authority record control number or standard number |
http://id.loc.gov/authorities/names/no2020030683 |
|
|---|
| Personal name |
Chmielewski, Slawomir. |
| Authority record control number or standard number |
http://id.loc.gov/authorities/names/n2015050372 |
| 852 ## - LOCATION |
|---|
| Piece designation |
10001000062116 |
| -- |
24553.00 |
| Classification part |
621.395 LOG 62116 |
| -- |
Hi-Tech Books |
| Sublocation or collection |
Ground Floor |
| Former shelving location |
Books |
| Copy number |
1 |
| Piece physical condition |
1-New |
| Location |
JZL-CUI |
